The present invention relates to a circuit comprised of semiconductor elements and, more particularly, to a circuit using insulated-gate, field-effect transistors which are realized as a semiconductor integrated circuit.
A dynamic random access memory ("RAM") employing insulated-gate field-effect transistors ("IGFET") frequently encounters an inner node charged to a power source V.sub.DD level which must by dynamically sustained. For example, the digit line of a RAM of one transistor memory cell type is charged up to the V.sub.DD level to prevent a refresh high level from falling, due to the activation of the dynamic sense amplifier. When a large capacity RAM is used, such as 64 k bit or more the level of the power source V.sub.DD must be decreased. The trend in the field is to increase the RAM memory capacity. The demand for this type of charging scheme is expected to increase.
At the present stage, the bootstrap capacitor raises the gate level of a charging IGFET above the V.sub.DD level. Such a rise of the gate level puts the IGFET in the non-saturated region so that the digit line is charged to the V.sub.DD level. This circuit, however, has no circuit function to keep the set level after the gate level is once set up above V.sub.DD. When subjected to a long period of timing cycle, the charge at the gate leaks off so that its potential levels downwardly. The result is that the charging level also falls. This adversely affects the operational margin. When the digit line in the single transistor memory type RAM is charged, the levels at both the input sides of the sense amplifier must be well balanced. Therefore, the gate level of the charging IGFET above the V.sub.DD must be stably maintained. The state of the balancing directly determines the operational margin. Some approach is needed to stabilize the charging level, therefore.